In circuit structure manufacturing, such as semiconductor device manufacturing, three-dimensional (3-D) integration can be achieved, for instance, using through substrate vias (TSVs) for chip stacking. Connecting or contact vias between the first metal level (or layer) and the TSVs is one useful method for achieving such integration, especially for 20 nm technology and below. Conventionally, there is a desire to achieve minimum pitch and minimum critical dimension (CD) for these contact vias to achieve as many connections as possible between the conductive structure (e.g., TSV) and first metal layer. Current practice for forming tightly packed connecting vias uses two reticles in a double-pattern process, in order to achieve the desired points of connectivity between the metal and TSV layers. In one application, the contacting vias are substantially identical and arrayed roughly uniformly over the contact surface of the TSV. In such an implementation, a “via opening” issue may arise depending, in part, on the circuit fabrication process flow.